One of the basic operational functions of a digital computer or a digital module data transfer system has to do with the integrity or reliability of the data being transferred. To this end, digital systems have generally been provided with one type or another of means for error checking or data parity checking in order to insure that data being transferred has not been corrupted.
As seen in FIG. 2, there is a block diagram of a data transfer system whereby data from a host processor 4 may be transferred to a Channel Interface Module (CIM) 8.sub.c and then transferred to a Device Interface Module (DIM) 8.sub.d from which the data can then be moved to one or more disk drive units 70.
During the course of such a data transfer operation, a block of data from the host processor 4 will be transferred down the channel interfaces 8.sub.c to the device interface 8.sub.d and then to the peripheral units, such as a disk drive module 70. The block of data transferred may take several different characteristics. For instance, as shown in FIG. 3A, a block of data composed of "X" bytes will have a header portion which may provide for the address of the destination and commands after which the main bulk of data is presented. This is followed by an error detection code (EDC) signature, which has been provided to the block of data in order to characterize the data being transmitted in the main block.
Likewise as seen in FIG. 3B, there may be a data block transfer of a different volume or size as shown by the block designated "Y" bytes. Here again, a header will provide the address destination, commands and other pertinent data after which the main body holds the data to be transferred followed by the Error Detection Code (EDC) signature which characterizes the data being transferred.
When a block of data, such as that of "X" bytes or that of "Y" bytes, is being transferred, it is necessary that some means be provided to recognize the block size and to insure the integrity of the data transfer. The reliability factor occurs when there is a certainty, that when the block of data has been transferred, the original sent data will be duplicated at the receipt point by the received data.
Various earlier methods of error detection and parity checking generally required detection circuitry which would analyze the data transferred to determine whether there was a proper transfer of data in an accurate fashion. These methods generally caused a delay in the transfer time for data movement, which acted to slow up the relative performance of the system.
As seen in FIG. 4, there is shown an example of two different block sizes which are to be transmitted between a sending and a receiving digital module, the first block size of 180 bytes, having a header and EDC signature, is followed by a larger block of 512 bytes, which also has its own personal header and EDC signature.
The present system operates to insure that there will be no delay in the data transfer operation even though blocks of different sizes are being transferred and the different block sizes will concurrently be checked for integrity without any delay to the data transfer operation.
As seen in FIG. 2B, the device interface module 8.sub.d (DIM) which is used to carry data to peripheral units, such as a disk drive unit 70, will be seen to have certain functioning modules which enhance the transfer of data to the peripheral units while at the same time providing for reliability in the data transfer by checking the integrity of the data being transferred. Thus, as seen in FIG. 2B, data which has been passed down from the channel interface 8.sub.c (CIM) and temporarily resides in the memory buffer 24.sub.d, will then be passed on bus 6 to a SCSI Protocol Controller (SPC) 80, which will provide management for transferring the data on bus 78 to a selected disk drive unit 70. The unit 70 may represent a multiple number of peripheral units which can receive blocks of data or send blocks of data.
As seen in FIG. 2B, the bus 6 between the memory buffer 24.sub.d and the protocol controller SPC 80, is also connected to an integrity circuit I.sub.c, 81. The integrity circuit 81 functions on-the-fly in order to check the integrity of the data being transferred. A control processor 10 provides initiation signals to the integrity circuit 81 so that it may provide its error checking function.
As illustrated in FIGS. 3A, 3B, blocks of data to be transferred can occur in different block sizes. FIG. 4 illustrates how each header of a block contains information as to the size of the block by denoting the number of bytes involved. Then after the pertinent data in the block is transmitted, the final portion of each block is seen to have an Error Detection Code (EDC) signature. This signature involves a Hexadecimal Code of, for example, of 9 bytes (36 bits) of which the first byte is a parity value (FIG. 4).